EENG 5550 - Hardware Design Methodologies for ASICs and FPGAs

3 hours

Explores hardware design methodologies through the use of industry tools. Students use design automation tools to design, simulate and synthesize designs for standard cell-based ASICs and FPGAs using hardware description languages (e.g., VHDL and Verilog). Examines the synthesis concept to understand how hardware functions written in these hardware description languages are synthesized. Covers techniques for design optimization, simulation, and synthesis of combinatorial functions, data paths, and finite state machines in depth. Examines the differences between design flows for standard cell-based ASICs and FPGAs.

Prerequisite(s): EENG 2710 or equivalent.